The present invention relates generally to a semiconductor memory device and a control apparatus, and, more particularly, to a data reading operation thereof.
Recently, faster data processing and lower power dissipation for electronic devices is in high demand. There is, therefore, a demand for faster data operation and lower power dissipation for semiconductor memory devices, one of various kinds of semiconductor integrated circuit devices installed in electronic devices.
FIG. 1 shows the essential portions of an ordinary read only semiconductor memory device (hereinafter referred to as "ROM") 60 which is installed in various types of electronic devices. The ROM 60 has memory cells of a NAND type. A plurality of cell blocks 61 are connected between a bit line BL and a low-voltage power supply GND. Each cell block 61 includes a single block select transistor comprised of an enhancement type N-channel MOS (NMOS) transistor, and three memory transistors.
There are two data reading operations for the ROM 60. One is a precharge operation and the other is a read operation which is performed after the precharge operation to read data.
When the precharge operation is initiated, a column switch 62 is set on to select a bit line BL, a cell block 61 is selected by a block select signal SL and a precharge P-channel MOS (PMOS) transistor 63 connected to a data line DL is enabled by a precharge signal PRE.
As shown in FIG. 2, as a current from a high-voltage power supply Vcc flows in the bit line BL, the bit line BL is precharged so that the potential of the bit line BL rises to a high potential. When the precharge signal PRE is disabled to terminate the precharge operation, the operation goes to the read operation.
In the read operation, when data in the memory transistor in the selected cell block 61 which is selected by a word signal is "0", the selected cell block 61 becomes conductive. This causes charges in the bit line BL to be discharged to the level of a low-voltage power supply GND via the selected cell block 61. Therefore, the potential of the bit line BL becomes a low potential (hereinafter called "L level"). The L-level potential of the bit line BL is output to an external unit as read data of "0" via an unillustrated sense amplifier connected to the data line DL.
In the read operation, when data in the selected memory transistor is "1", the selected cell block 61 becomes nonconductive. Therefore, charges in the bit line BL will not be discharged to the level of the low-voltage power supply GND via the selected cell block 61. In this case, the potential of the bit line BL becomes a high potential (hereinafter called "H level"). The H-level potential of the bit line BL is output to the external unit as read data of "1" via the unillustrated sense amplifier connected to the data line DL.
FIG. 3 shows the essential portions of another typical ROM 70. The ROM 70, like the ROM 60, has memory cells of a NAND type. Each cell block 71 includes a single block select transistor comprised of an enhancement type N-channel MOS (NMOS) transistor, three memory transistors, and a single discharge transistor.
When the precharge operation of the ROM 70 is initiated, a column switch 72 is set on to select a bit line BL, a cell block 71 is selected by a block select signal SL and a precharge PMOS transistor 73 connected to a data line DL is enabled by a precharge signal PRE. At this time, the discharge transistor is set off by a discharge signal XPRE.
As shown in FIG. 4, as a current from a high-voltage power supply V.sub.CC flows in the bit line BL, the bit line BL is precharged so that the potential of the bit line BL rises to a high potential. When a precharge cycle ends by disabling the precharge signal PRE, the discharge transistor is set on by a discharge signal XPRE and the operation goes to the read operation.
In the read operation, when data in the memory transistor in the selected cell block 71 which is selected by a word signal is "0", the selected cell block 71 becomes conductive. This causes charges in the bit line BL to be discharged to the level of a low-voltage power supply GND via the selected cell block 71. Therefore, the potential of the bit line BL becomes an L level. The L-level potential of the bit line BL is output to an external unit as read data of "0" via an unillustrated sense amplifier connected to the data line DL.
In the read operation, when data in the memory transistor in the selected cell block 71 which is selected by the word signal is "1", the selected cell block 71 becomes nonconductive. Therefore, charges in the bit line BL will not be discharged to the level of the low-voltage power supply GND via the selected cell block 71. In this case, the potential of the bit line BL becomes an H level. The H-level potential of the bit line BL is output to the external unit as read data of "1" via the unillustrated sense amplifier connected to the data line DL.
In the ROM 60 shown in FIG. 1, charges in the bit line BL are discharged to the level of the low-voltage power supply GND via the selected cell block 61 even in the precharge operation when data in the selected memory transistor is "0". In the read operation, therefore, the potential of the bit line BL becomes an L level quickly. As a result, the ROM 60 can shorten the time for establishing data and is thus suitable for a fast operation. Because discharging is carried out in the ROM 60 even in the precharge operation, however, the ROM suffers large current consumption which becomes a problem particularly in a slow operation.
In the ROM 70 shown in FIG. 3, by contrast, when data in the selected memory transistor is "0", charges in the bit line BL are not discharged to the level of the low-voltage power supply GND via the selected cell block 71 until the precharge operation is finished. The ROM 70 is therefore advantageous over the ROM 60 in FIG. 1 in reducing the current consumption.
Because no discharge is performed in the ROM 70 in the precharge operation, however, the bit line BL is charged up to the level of the high-voltage power supply V.sub.CC. When the discharge transistor is turned on to read data of "0" from the selected memory transistor in the read operation, the discharging starts at the level of the high-voltage power supply V.sub.CC. It therefore takes a long time for the potential of the bit line BL to reach the L level. The ROM 70 thus needs a longer time to establish data and is thus, not suitable for a fast operation.
As previously discussed, various kinds of electronic devices demand low power dissipation and high speed. To meet this demand, only the minimum essential semiconductor integrated circuit devices are enabled when each electronic device is not in use, and the operational speed of the enabled semiconductor integrated circuit devices is set low, thereby decreasing the current dissipation. It would therefore be desirable to have a ROM which can operate both fast and slowly.
As mentioned above, however, the conventional ROM 60 shown in FIG. 1 cannot provide a reduction in power consumption in a slow operation mode. By contrast, the conventional ROM 70 shown in FIG. 3 is not suitable for a fast operation.